The present invention relates to an A/D converter, digital PLL circuit, and information recording apparatus and, more particularly, to a digital PLL circuit which generates a recording clock, is suitably integrated into an LSI, and utilized in an information recording apparatus for an optical disk, and an information recording apparatus using the same.
Recording media represented by a CD (Compact Disc) and DVD (Digital Versatile Disc) can hold a large amount of information and process so-called AV (Audio-Visual) information. In recent years, information recording/playback apparatuses using such recording media have rapidly prevailed as a peripheral device of a personal computer and the like. In this situation, a recordable disk standard for a CD-R/RW, DVD-R/RW and DVD−R/RW must keep continuity between a recorded pit string and a newly recorded pit string in order to enable playback by a ROM player after recording.
For this purpose, tracking guide grooves which wobble at a specific frequency are formed in advance as pregrooves on such recording medium. In recording information, a wobble signal obtained from a wobbling tracking guide groove is read out, a recording clock phase-locked with the wobble signal is generated, and information is recorded. The wobble signal frequency is set in a high band exceeding the servo band of an optical head actuator and a band lower than the frequency band of recording information. This setting allows detecting a wobble signal even during tracking, and can increase the wobble signal quality.
For example, a DVD+R/RW has a wobble signal cycle 32 times longer than the recording clock cycle, and a DVD−R/RW has a wobble signal cycle 186 times longer than the recording clock cycle. By recording information by a recording clock synchronized with a wobble signal, information can be recorded at a correct position even with decentering of the disk. Even in sequential write, the phase precision of a wobble signal at the link can fall within a cycle of several recording clocks.
However, the quality of a wobble signal degrades owing to the presence/absence of information pit recording, contamination of the disk surface, and deterioration of the optical head. There has been proposed a digital signal processing technique of extracting a high-precision clock while compensating for degradation of the quality.
More specifically, the center frequency of a VCO (Voltage Controlled Oscillator) in a PLL (Phase Locked Loop) circuit is changed in accordance with externally supplied frequency information and timing information. The center frequency of a narrow-band BPF (Band Pass Filter) for limiting the band of an input signal is changed on the basis of a sync clock output from the PLL circuit. There has also been proposed a method of increasing the SNR (Signal-to-Noise Ratio) of a wobble signal by applying a digital signal process to the above-described technique (see Japanese Patent Laid-Open No. 2003-115174). The PLL circuit which generates a recording clock from a wobble signal is important because it determines the information recording quality of the disk.
In order to downsize the drive device and improve its reliability, the number of components must be decreased. At present, circuits which are distributed to several LSI (Large Scale Integrated circuit) chip sets have been developed to shrink into one chip set in the future. In this case, high stability, high yield, and low power consumption are important. When a full-digital PLL is integrated into an LSI, the same characteristic can be attained. However, a conventional configuration using an analog PLL suffers a change in PLL loop characteristic depending on the temperature characteristic or the like, and it is difficult to decrease the difference between LSIS. Thus, when an analog PLL is employed, for example, a PLL loop is constructed by adding a function of correcting the VCO temperature characteristic which is known in advance from an output from the temperature sensor (see Japanese Patent Laid-Open No. 2002-217720).
A digital PLL including a digital VCO requires a high-frequency operating clock because the digital PLL cannot obtain a phase resolution equal to or lower than the operating clock cycle. To avoid this, there have been proposed a configuration using a D/A converter and analog VCO (see Japanese Patent Laid-Open No. 2002-217720), and a method using a D/A converter and a DDS (Direct Digital frequency Synthesizer) by an SIN table (see Japanese Patent Laid-Open No. 11-31924).
However, a full-digital PLL using only an A/D converter and digital circuit, as shown in FIG. 8, is becoming feasible because of the following two reasons. First, the circuit operating speed increases with the advance of the LSI process technique. Second, a technique of increasing the phase precision by modulating the phase of an output clock edge without increasing the VCO operating clock has been developed (see Japanese Patent Laid-Open No. 2003-209468). As shown in FIG. 8, a conventionally proposed digital PLL circuit is formed from a high-bit resolution A/D (high-bit RAD) 100 with a bit width of 8 bits or the like, a low-pass digital filter 2, a sampler 3, a digital phase comparator 5, a digital loop filter 6, and a digital VCO 7. The high-bit resolution A/D 100 operates on the basis of a signal output from the digital VCO 7 or its frequency-divided signal as a clock.
Speedup competition for recording in a recordable DVD heats up now. For an N-time speed, the rotational speed of the disk is N times, and the digital circuit system must also operate at the N-time speed. This is inhibited by particularly the operation of the A/D converter in the above-mentioned digital PLL circuit. For example, for a DVD+R of 12×CAV (Constant Angular Velocity) operation, the wobble frequency at the outermost track is 24 MHz. A process such as digital BPF requires sampling of at least 96 Msps (sampling per second) which is four times higher than the wobble frequency. Thus, the circuit of the A/D converter comes to large scale because of digitization at about 8 bits.
The first problem to be solved is that when a digital PLL is mounted on an LSI, a high-speed A/D converter with a large circuit scale is necessary, and it is difficult to lay out the A/D converter together with another block. The second problem is that power consumption increases, it becomes difficult to dissipate heat, and the yield decreases because a high-speed A/D converter is necessary.